As semiconductor manufacturing technologies continue to evolve toward smaller design rules and higher integration densities (e.g., 14 nm technology node and beyond), integrated circuit devices and components become increasingly smaller, creating challenges in layout formation and device optimization. Currently, FinFET technologies are typically implemented for FET fabrication, as such technologies provide effective CMOS scaling solutions for FET fabrication at, and below, the 14 nm technology node. A FinFET device comprises a three-dimensional fin-shaped FET structure which includes at least one vertical semiconductor fin formed on a substrate, a gate structure formed over a portion of the vertical semiconductor fin, and source/drain layers formed from portions of the vertical semiconductor fin extending from both sides of the gate structure. The portion of the vertical semiconductor fin that is covered by the gate structure between the source/drain layers comprises a channel region of the FinFET device.
The ability to fabricate vertical semiconductor fins having uniform profiles has proven to be challenging and non-trivial using current FinFET process technologies. For example, in a typical bulk FinFET process flow in which semiconductor fins are formed on a surface of a semiconductor substrate, a shallow trench isolation (STI) layer is formed to cover bottom portions of vertical semiconductor fins to provide an isolation layer which isolates the FinFET device elements (e.g., gates, source/drain layers, etc.) from the bulk substrate. However, during a gate oxide etch process (e.g., removing a dummy gate oxide), the exposed portions of the STI layer will be etched and recessed, resulting in non-uniform heights of the vertical semiconductor fins across the device regions of the wafer or chip. This undesired recessing of the STI layer during the oxide etch is even more problematic when semiconductor fin profile thinning techniques are applied to decrease the width of the active portions of the vertical semiconductor fins which extend above the STI layer. In this instance, the active fin profile of the FinFET devices will include the thinned portions of the vertical semiconductor fins, as well as a portion of the non-thinned portion of the vertical semiconductor fins due to the additional recess of the STI layer. This results in FinFET devices with non-uniform fin profiles as well as gate structures with a large effective oxide thickness (EOT) which creates undesired leakage paths. This situation is even more problematic when over-etch is needed to remove thick thermal oxide layers and the etch rate selectivity between the thermal oxide material and the STI oxide material is poor, such that significant STI oxide loss will occur.